GTIOR

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Interpret as GTIOR

OADF=00, OBE=0, GTIOA=00000, OADFLT=0, GTIOB=00000, NFAEN=0, OBDF=00, OAE=0, OBHLD=0, OAHLD=0, NFCSB=00, NFBEN=0, OBDFLT=0, NFCSA=00

Description

General PWM Timer I/O Control Register

Fields

GTIOA	GTIOCA Pin Function Select 0 (00000): Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. 1 (00001): Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. 2 (00010): Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. 3 (00011): Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. 4 (00100): Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. 5 (00101): Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. 6 (00110): Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. 7 (00111): Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. 8 (01000): Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. 9 (01001): Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. 10 (01010): Initial output is Low. High output at cycle end. High output at GTCCRA compare match. 11 (01011): Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. 12 (01100): Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. 13 (01101): Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. 14 (01110): Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. 15 (01111): Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. 16 (10000): Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. 17 (10001): Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. 18 (10010): Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. 19 (10011): Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. 20 (10100): Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. 21 (10101): Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. 22 (10110): Initial output is High. Low output at cycle end. High output at GTCCRA compare match. 23 (10111): Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. 24 (11000): Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. 25 (11001): Initial output is High. High output at cycle end. Low output at GTCCRA compare match. 26 (11010): Initial output is High. High output at cycle end. High output at GTCCRA compare match. 27 (11011): Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. 28 (11100): Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. 29 (11101): Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. 30 (11110): Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. 31 (11111): Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match.
OADFLT	GTIOCA Pin Output Value Setting at the Count Stop 0 (0): Output low on GTIOCA pin when counting stops 1 (1): Output high on GTIOCA pin when counting stops.
OAHLD	GTIOCA Pin Output Setting at the Start/Stop Count 0 (0): Set GTIOCA pin output level on counting start and stop based on the register setting. 1 (1): Retain GTIOCA pin output level on counting start and stop
OAE	GTIOCA Pin Output Enable 0 (0): Disable output 1 (1): Enable output.
OADF	GTIOCA Pin Disable Value Setting 0 (00): Prohibit output disable 1 (01): Set GTIOCA pin to Hi-Z on output disable 2 (10): Set GTIOCA pin to 0 on output disable 3 (11): Set GTIOCA pin to 1 on output disable.
NFAEN	Noise Filter A Enable 0 (0): Disable noise filter for GTIOCA pin 1 (1): Enable noise filter for GTIOCA pin.
NFCSA	Noise Filter A Sampling Clock Select 0 (00): PCLK/1 1 (01): PCLK/4 2 (10): PCLK/16 3 (11): PCLK/64
GTIOB	GTIOCB Pin Function Select 0 (00000): Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. 1 (00001): Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. 2 (00010): Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. 3 (00011): Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. 4 (00100): Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. 5 (00101): Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. 6 (00110): Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. 7 (00111): Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. 8 (01000): Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. 9 (01001): Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. 10 (01010): Initial output is Low. High output at cycle end. High output at GTCCRB compare match. 11 (01011): Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. 12 (01100): Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. 13 (01101): Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. 14 (01110): Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. 15 (01111): Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. 16 (10000): Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. 17 (10001): Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. 18 (10010): Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. 19 (10011): Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. 20 (10100): Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. 21 (10101): Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. 22 (10110): Initial output is High. Low output at cycle end. High output at GTCCRB compare match. 23 (10111): Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. 24 (11000): Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. 25 (11001): Initial output is High. High output at cycle end. Low output at GTCCRB compare match. 26 (11010): Initial output is High. High output at cycle end. High output at GTCCRB compare match. 27 (11011): Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. 28 (11100): Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. 29 (11101): Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. 30 (11110): Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. 31 (11111): Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match.
OBDFLT	GTIOCB Pin Output Value Setting at the Count Stop 0 (0): Output low on GTIOCB pin when counting stops 1 (1): Output high on GTIOCB pin when counting stops
OBHLD	GTIOCB Pin Output Setting at the Start/Stop Count 0 (0): Set GTIOCB pin output level on counting start and stop based on the register setting 1 (1): Retain GTIOCB pin output level on counting start and stop
OBE	GTIOCB Pin Output Enable 0 (0): Disable output 1 (1): Enable output
OBDF	GTIOCB Pin Disable Value Setting 0 (00): Prohibit output disable 1 (01): Set GTIOCB pin to Hi-Z on output disable 2 (10): Set GTIOCB pin to 0 on output disable 3 (11): Set GTIOCB pin to 1 on output disable.
NFBEN	Noise Filter B Enable 0 (0): Disable noise filter for GTIOCB pin 1 (1): Enable noise filter for GTIOCB pin
NFCSB	Noise Filter B Sampling Clock Select 0 (00): PCLK/1 1 (01): PCLK/4 2 (10): PCLK/16 3 (11): PCLK/64

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